View 70V3589S133BCGI_9023639.PDF datasheet online --- IC-ON-LINE

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?20104 integrated device technology, inc. october 2014 dsc 5617/10 1 ? functional block diagram features: true dual-port memory cells which allow simultaneous access of the same memory location high-speed data access ? commercial: 3.6ns (166mhz)/4.2ns (133mhz) (max.) ? industrial: 4.2ns (133mhz) (max.) selectable pipelined or flow-through output mode counter enable and repeat features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 6ns cycle time, 166mhz operation (12gbps bandwidth) ? fast 3.6ns clock to data out ? 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166mhz ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus matching compatibility dual cycle deselect (dcd) for pipelined output mode lvttl- compatible, 3.3v (150mv) power supply for core lvttl compatible, selectable 3.3v (150mv) or 2.5v (100mv) power supply for i/os and control signals on each port industrial temperature range (-40c to +85c) is available at 133mhz. available in a 208-pin plastic quad flatpack (pqfp), 208-pin fine pitch ball grid array (fpbga), and 256-pin ball grid array (bga) supports jtag features compliant with ieee 1149.1 green parts available, see ordering information high-speed 3.3v 128/64k x 36 synchronous dual-port static ram with 3.3v or 2.5v interface idt70v3599/89s repeat r a 16r (1) a 0r cnten r ads r dout0-8_r dout9-17_r i/o 0r - i/o 35r din_r addr_r oe r be r be 2r be 1r be 0r r/ w r ce 0r ce 1r 1 0 1/0 ft /pipe r 1a 0a 1b 0b 1c 0c 1d 0d dcba clk r , counter/ address reg. dcba 0/1 0d 1d 0c 1c 0b 1b 0a 1a b w 2 r b w 1 r b w 0 r ft /pipe r counter/ address reg. cnten l ads l repeat l dout0-8_l dout9-17_l dout18-26_l dout27-35_l dout18-26_r dout27-35_r b w 0 l b w 1 l b w 2 l b w 3 l i/o 0l -i/o 35 l a 16l (1) a 0l din_l addr_l oe l 5617 tbl 01 be 3l be 2l be 1l be 0l r/ w l ce 0l ce 1l 128k x 36 memory array clk l abcd ft /pipe l 0/1 1d 0d 1c 0c 1b 0b 1a 0a b w 3 r jtag tck trst tms tdo tdi 1 0 1/0 0d 1d 0c 1c 0b 1b 0a 1a abcd ft /pipe l 1/0 1/0 note: 1. a 16 is a nc for idt70v3589.
6.42 2 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s description: the idt70v3599/89 is a high-speed 128/64k x 36 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70v3599/89 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. the 70v3599/89 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device (v dd ) remains at 3.3v. pin configuration (1,2,3,4,5) notes: 1. a 16 is a nc for idt70v3589. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. a17 v ss b17 i/o 15r c17 v ss d17 i/o 14r e16 v ss e17 i/o 13l d16 i/o 14l c16 i/o 15l b16 i/o 16l a16 i/o 17l a15 opt l b15 v ddqr c15 i/o 16r d15 v ddql e15 i/o 13r e14 i/o 12l d14 i/o 17r d13 v dd c12 a 6l c14 v dd b14 v ss a14 a 0l a12 cnten l b12 a 5l c11 r/ w l d12 a 3l d11 repeat l c10 v ss b11 ads l a11 clk l d8 be 0l c8 be 3l a9 be 1l d9 v dd c9 ce 1l b9 ce 0l d10 oe l c7 a 10l b8 be 2l a8 a 8l b13 a 1l a13 a 4l a10 v dd d7 a 7l b7 a 9l a7 a 12l b6 a 13l c6 a 14l d6 a 11l a5 nc b5 nc c5 nc d5 a 15l a4 tdo b4 tdi c4 pl/ ft l d4 i/o 20l a3 v ss b3 i/o 18r c3 v ddqr d3 i/o 21l d2 v ss c2 i/o 19r b2 v ss a2 io 18l a1 io 19l b1 i/o 20r c1 v ddql d1 i/o 22l e1 i/o 23l e2 i/o 22r e3 v ddqr e4 i/o 21r f1 v ddql f2 i/o 23r f3 i/o 24l f4 v ss g1 i/o 26l g2 v ss g3 i/o 25l g4 i/o 24r h1 v dd h2 i/o 26r h3 v ddqr h4 i/o 25r j1 v ddql j2 v dd j3 v ss j4 v ss k1 i/o 28r k2 v ss k3 i/o 27r k4 v ss l1 i/o 29r l2 i/o 28l l3 v ddqr l4 i/o 27l m1 v ddql m2 i/o 29l m3 i/o 30r m4 v ss n1 i/o 31l n2 v ss n3 i/o 31r n4 i/o 30l p1 i/o 32r p2 i/o 32l p3 v ddqr p4 i/o 35r r1 v ss r2 i/o 33l r3 i/o 34r r4 tck t1 i/o 33r t2 i/o 34l t3 v ddql t4 tms u1 v ss u2 i/o 35l u3 pl/ ft r u4 nc p5 trst r5 nc u6 a 11r p12 cnten r p8 a 8r u10 oe r p9 be 1r r8 be 2r t8 be 3r u9 v dd p10 v dd t11 r/ w r u8 be 0r p11 clk r r12 a 5r t12 a 6r u12 a 3r p13 a 4r p7 a 12r r13 a 1r t13 a 2r u13 a 0r r6 a 13r t5 nc u7 a 7r u14 v dd t14 v ss r14 v ss p14 i/o 2l p15 i/o 3l r15 v ddql t15 i/o 0r u15 opt r u16 i/o 0l u17 i/o 1l t16 v ss t17 i/o 2r r17 v ddqr r16 i/o 1r p17 i/o 4l p16 v ss n17 i/o 5l n16 i/o 4r n15 v ddql n14 i/o 3r m17 v ddqr m16 i/o 5r m15 i/o 6l m14 v ss l17 i/o 8l l16 v ss l15 i/o 7l l14 i/o 6r k17 v ss k16 i/o 8r k15 v ddql k14 i/o 7r j17 v ddqr j16 v ss j15 v dd j14 v ss h17 i/o 10r h16 v ss h15 io 9r h14 v dd g17 i/o 11r g16 i/o 10l g15 v ddql g14 i/o 9l f17 v ddqr f16 i/o 11l f14 v ss 70v3599/89bf bf-208 (6) 208-pin fpbga top view (7) f15 i/o 12r r9 ce 0r r11 ads r t6 a 14r t9 ce 1r a6 a 16l (1) b10 v ss c13 a 2l p6 a 16r (1) r10 v ss r7 a 9r t10 v ss t7 a 10r u5 a 15r 5617 drw 02c , 06/28/02
6.42 3 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s pin configuration (1,2,3,4,5) (con't.) notes: 1. a 16 is a nc for idt70v3589. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 70v3599/89bc bc-256 (6) 256-pin bga top view (7) e16 i/o 14r d16 i/o 16r c16 i/o 16l b16 nc a16 nc a15 nc b15 i/o 17l c15 i/o 17r d15 i/o 15l e15 i/o 14l e14 i/o 13l d14 i/o 15r d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b11 repeat l a11 cnten l d8 v ddqr c8 be 1l a9 ce 1l d9 v ddql c9 be 0l b9 ce 0l d10 v ddql c7 a 7l b8 be 3l a8 be 2l b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 nc b4 nc c4 a 16l (1) d4 pipe/ ft l a3 nc b3 tdo c3 v ss d3 i/o 20l d2 i/o 19r c2 i/o 19l b2 nc a2 tdi a1 nc b1 i/o 18l c1 i/o 18r d1 i/o 20r e1 i/o 21r e2 i/o 21l e3 i/o 22l e4 v ddql f1 i/o 23l f2 i/o 22r f3 i/o 23r f4 v ddql g1 i/o 24r g2 i/o 24l g3 i/o 25l g4 v ddqr h1 i/o 26l h2 i/o 25r h3 i/o 26r h4 v ddqr j1 i/o 27l j2 i/o 28r j3 i/o 27r j4 v ddql k1 i/o 29r k2 i/o 29l k3 i/o 28l k4 v ddql l1 i/o 30l l2 i/o 31r l3 i/o 30r l4 v ddqr m1 i/o 32r m2 i/o 32l m3 i/o 31l m4 v ddqr n1 i/o 33l n2 i/o 34r n3 i/o 33r n4 pipe/ ft r p1 i/o 35r p2 i/o 34l p3 tms p4 a 16r (1) r1 i/o 35l r2 nc r3 trst r4 nc t1 nc t2 tck t3 nc t4 nc p5 a 13r r5 a 15r p12 a 6r p8 be 1r p9 be 0r r8 be 3r t8 be 2r p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 i/o 0l p15 i/o 0r r15 nc t15 nc t16 nc r16 nc p16 i/o 1l n16 i/o 2r n15 i/o 1r n14 i/o 2l m16 i/o 4l m15 i/o 3l m14 i/o 3r l16 i/o 5r l15 i/o 4r l14 i/o 5l k16 i/o 7l k15 i/o 6l k14 i/o 6r j16 i/o 8l j15 i/o 7r j14 i/o 8r h16 i/o 10r h15 io 9l h14 i/o 9r g16 i/o 11r g15 i/o 11l g14 i/o 10l f16 i/o 12l f14 i/o 12r f15 i/o 13r r9 ce 0r r11 repeat r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 v ss f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 v ss j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 v ss j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 v ss l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5617 drw 02d , 06/28/02
6.42 4 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s pin configuration (1,2,3,4,5) (con't.) notes: 1. a16 is a nc for idt70v3589. 2. all v dd pins must be connected to 3.3v power supply. 3. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 4. all v ss pins must be connected to ground supply. 5. package body is approximately 28mm x 28mm x 3.5mm. 6. this package code is used to reference the package diagram. 7. this text does not indicate orientation of the actual part-marking. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 2 0 8 2 0 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 2 0 1 2 0 0 1 9 9 1 9 8 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 1 9 1 1 9 0 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 1 6 9 1 6 8 1 6 7 1 6 6 1 6 5 1 6 4 1 6 3 1 6 2 1 6 1 1 6 0 1 5 9 1 5 8 1 5 7 70v3599/89dr dr-208 (6) 208-pin pqfp top view (7) i/o 19l i/o 19r i/o 20l i/o 20r v ddql v ss i/o 21l i/o 21r i/o 22l i/o 22r v ddqr v ss i/o 23l i/o 23r i/o 24l i/o 24r v ddql v ss i/o 25l i/o 25r i/o 26l i/o 26r v ddqr v ss v dd v dd v ss v ss v ddql v ss i/o 27r i/o 27l i/o 28r i/o 28l v ddqr v ss i/o 29r i/o 29l i/o 30r i/o 30l v ddql v ss i/o 31r i/o 31l i/o 32r i/o 32l v ddqr v ss i/o 33r i/o 33l i/o 34r i/o 34l v s s v d d q l i / o 3 5 r i / o 3 5 l p l / f t r t m s t c k t r s t n c n c n c a 1 6 r ( 1 ) a 1 5 r a 1 4 r a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r b e 3 r b e 2 r b e 1 r b e 0 r c e 1 r c e 0 r v d d v d d v s s v s s c l k r o e r r / w r a d s r c n t e n r r e p e a t r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r v d d v s s v s s o p t r i / o 0 l i / o 0 r v d d q l v s s i/o 16l i/o 16r i/o 15l i/o 15r v ss v ddql i/o 14l i/o 14r i/o 13l i/o 13r v ss v ddqr i/o 12l i/o 12r i/o 11l i/o 11r v ss v ddql i/o 10l i/o 10r i/o 9l i/o 9r v ss v ddqr v dd v dd v ss v ss v ss v ddql i/o 8r i/o 8l i/o 7r i/o 7l v ss v ddqr i/o 6r i/o 6l i/o 5r i/o 5l v ss v ddql i/o 4r i/o 4l i/o 3r i/o 3l v ss v ddqr i/o 2r i/o 2l i/o 1r i/o 1l v s s v d d q r i / o 1 8 r i / o 1 8 l v s s p l / f t l t d i t d o n c n c n c a 1 6 l ( 1 ) a 1 5 l a 1 4 l a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l b e 3 l b e 2 l b e 1 l b e 0 l c e 1 l c e 0 l v d d v d d v s s v s s c l k l o e l r / w l a d s l c n t e n l r e p e a t l a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l v d d v d d v s s o p t l i / o 1 7 l i / o 1 7 r v d d q r v s s 5617 drw 02a , 06/28/02
6.42 5 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s pin names left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (5) r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 16 l (1) a 0r - a 16r (1 ) address i/o 0l - i/o 35l i/o 0r - i/o 35r data input/outp ut clk l clk r clock pl/ ft l pl/ ft r pipeline/flow-through ads l ad s r address strobe enable cnten l cnten r counter enable repeat l repeat r counter repeat (4) be 0l - be 3l be 0r - be 3r byte enables (9-bit bytes) (5) v dd q l v ddqr power (i/o bus) (3.3v or 2.5v) (2) opt l opt r op tio n fo r se le cting v ddqx (2,3) v dd power (3.3v) (2 ) v ss ground (0v) tdi te st data inp ut tdo te st data outp ut tck test logic clock (10mhz) tms test mode select trst re se t (initialize tap controlle r) 5617 tbl 01 notes: 1. a 16 is a nc for idt70v3589. 2. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 3. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to vih (3.3v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to vil (0v), then that port's i/os and address controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 4. when repeat x is asserted, the counter will reset to the last valid address loaded via ads x . 5. chip enables and byte enables are double buffered when pl/ ft = v ih , i.e., the signals take two cycles to deselect.
6.42 6 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , repeat = x. 3. oe is an asynchronous input signal. 4. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table i?read/write and enable control (1,2,3,4) oe clk ce 0 ce 1 be 3 be 2 be 1 be 0 r/ w byte 3 i/o 27-35 byte 2 i/o 18-26 byte 1 i/o 9-17 byte 0 i/o 0-8 mode x hxxxxxxhigh-zhigh-zhigh-zhigh-zdeselected?power down x xlxxxxxhigh-zhigh-zhigh-zhigh-zdeselected?power down x l h h h h h x high-z high-z high-z high-z all bytes deselected x l h h h h l l high-z high-z high-z d in write to byte 0 only x lhhhlhlhigh-zhigh-z d in high-z write to byte 1 only x lhhlhhlhigh-z d in high-z high-z write to byte 2 only x lhlhhhl d in high-z high-z high-z write to byte 3 only x l h h h l l l high-z high-z d in d in write to lower 2 bytes only x lhllhhl d in d in high-z high-z write to upper 2 bytes only x lhlllll d in d in d in d in write to all bytes l l h h h h l h high-z high-z high-z d out read byte 0 only l lhhhlhhhigh-zhigh-z d out high-z read byte 1 only l lhhlhhhhigh-z d out high-z high-z read byte 2 only l lhlhhhh d out high-z high-z high-z read byte 3 only l lhhhllhhigh-zhigh-z d out d out read lo wer 2 byte s only l lhllhhh d out d out high-z high-z read upper 2 bytes only l lhllllh d out d out d out d out read all bytes h lhllllxhigh-zhigh-zhigh-zhigh-zoutputs disabled 5617 tbl 0 2 truth table ii?address counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , be n and oe . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ads and repeat are independent of all other memory control signals including ce 0 , ce 1 and be n 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , be n. 6. when repeat is asserted, the counter will reset to the last valid address loaded via ads . this value is not set at power-up: a known location should be loaded via ads during initialization if desired. any subsequent ads access during operations will update the repeat address location. external address previous internal address internal address used clk ads cnten repeat (6) i/o (3) mode xxan xx l (4) d i/o (0) counter reset to last valid ads load an x an l (4) xhd i/o (n) external address used an ap ap hh h d i/o (p) external address blocked?counter disabled (ap reused) xapap + 1 h l (5) hd i/ o (p+1) counter enabled?internal address generation 5617 t bl 03
6.42 7 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s recommended operating temperature and supply voltage (1) recommended dc operating conditions with v ddq at 2.5v absolute maximum ratings (1) notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 100mv. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v il (0v), and v ddqx for that port must be supplied as indicated above. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. 3. ambient temperature under bias. no ac conditions. chip deselected. notes: 1. this is the parameter ta. this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 5617 tbl 04 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supp ly voltage (3 ) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage (address & control inputs) 1.7 ____ v ddq + 100mv (2 ) v v ih input high voltage - i/o (3) 1.7 ____ v ddq + 100mv (2 ) v v il input low voltage -0.3 (1) ____ 0.7 v 5617 tbl 05a symbol rating commercial & industrial unit v term (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 5617 tbl 06 recommended dc operating conditions with v ddq at 3.3v notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v ddq + 150mv. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ih (3.3v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih inp ut hig h vo ltage (address & control inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih inp ut hig h vo ltage - i/o (3) 2.0 ____ v ddq + 150mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v 5617 tbl 05b
6.42 8 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 150mv) note: 1. at v dd < 2.0v leakages are undefined. 2. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.5 for details. symbol parameter test conditions 70v3599/89s unit min. max. |i li | input leakage current (1 ) v ddq = max., v in = 0v to v ddq ___ 10 a |i lo | output leakage current (1) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (2) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (2 ) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (2) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (2 ) i oh = -2ma, v ddq = min. 2.0 ___ v 5617 tbl 08 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) pqfp only symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 8 pf c out (3) output capacitance v out = 3dv 10.5 pf 5617 tbl 07
6.42 9 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 3.3v 150mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddq - 0.2v ce x > v ddq - 0.2v means ce 0x > v ddq - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 70v3599/89s166 com'l only 70v3599/89s133 com'l & ind symbol parameter test condition version typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 370 500 320 400 ma ind s ____ ____ 320 480 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih, outputs disabled, f = f max (1) com'l s 125 200 115 160 ma ind s ____ ____ 115 195 i sb2 standby current (one po rt - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (1) com'l s 250 350 220 290 ma ind s ____ ____ 220 350 i sb3 full standby current (both ports - cmos level inputs) both ports outputs disabled ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'l s 15 30 15 30 ma ind s ____ ____ 15 40 i sb4 full standby current (one po rt - cmos level inputs) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l s 250 350 220 290 ma ind s ____ ____ 220 350 5617 tbl 09
6.42 10 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s ac test conditions (v ddq - 3.3v/2.5v) figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels (address & controls) input pulse lev els (i/os) input ris e/fall times input timing re fe renc e lev els output reference levels output load gnd to 3 . 0v/gnd to 2.4v gnd to 3.0v/gnd to 2.4v 2ns 1.5v/1.25v 1.5v/1.25v figures 1 and 2 5617 tbl 10 1.5v/1.25 50 50 5617 drw 03 10pf (tester) data out , 5617 drw 04 590 5pf* 435 3.3v data out , 833 5pf* 770 2.5v data out , -1 1 2 3 4 5 6 7 20.5 30 50 80 100 200 10.5pf is the i/o capacitance of this device, and 10pf is the ac test load capacitance. capacitance (pf) tcd (typical, ns) 5617 drw 05 ? ? ? ? ,
6.42 11 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s ac electrical characteristics over the operating temperature range (read and write cycle timing) (2,3) (v dd = 3.3v 150mv) notes: 1. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe x = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 2. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ) and ft /pipe. ft /pipe should be treated as a dc signal, i.e. steady state during operation. 3. these values are valid for either level of v ddq (3.3v/2.5v). see page 5 for details on selecting the desired operating voltage levels for each port. 70v3599/89s166 com'l only 70v3599/89s133 com'l & ind symbol parameter min. max. min. max. unit t cyc1 clock cycle time (flow-through) (1) 20 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (1) 6 ____ 7.5 ____ ns t ch1 clock high time (flow-through) (1) 6 ____ 7 ____ ns t cl1 clock lo w time (flo w-thro ug h) (1) 6 ____ 7 ____ ns t ch2 clock high time (pipelined) (2) 2.1 ____ 2.6 ____ ns t cl2 clock low time (pipelined) (1) 2.1 ____ 2.6 ____ ns t sa address setup time 1.7 ____ 1.8 ____ ns t ha address hold time 0.5 ____ 0.5 ____ ns t sc chip enable setup time 1.7 ____ 1.8 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ ns t sb byte enable setup time 1.7 ____ 1.8 ____ ns t hb byte enable hold time 0.5 ____ 0.5 ____ ns t sw r/w setup time 1.7 ____ 1.8 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ ns t sd input data se tup time 1.7 ____ 1.8 ____ ns t hd input data ho ld time 0.5 ____ 0.5 ____ ns t sad ads setup time 1.7 ____ 1.8 ____ ns t had ads hold time 0.5 ____ 0.5 ____ ns t scn cnten setup time 1.7 ____ 1.8 ____ ns t hcn cnten hold time 0.5 ____ 0.5 ____ ns t srpt repeat setup time 1.7 ____ 1.8 ____ ns t hrpt repeat hold time 0.5 ____ 0.5 ____ ns t oe output enable to data valid ____ 4.0 ____ 4.2 ns t olz output enable to output low-z 1 ____ 1 ____ ns t ohz output enable to output high-z 1 3.6 1 4.2 ns t cd1 clock to data valid (flow-through) (1) ____ 12 ____ 15 ns t cd2 clock to data valid (pipelined) (1) ____ 3.6 ____ 4.2 ns t dc data outp ut ho ld afte r clock high 1 ____ 1 ____ ns t ckhz clock hig h to outp ut hig h-z 1 3 1 3 ns t cklz clock hig h to outp ut lo w-z 1 ____ 1 ____ ns port-to-port delay t co clock-to-clock offset 5 ____ 6 ____ ns 5617 tbl 11
6.42 12 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 be n (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5617 drw 06 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) timing waveform of read cycle for pipelined operation ( ft /pipe 'x' = v ih ) (2) notes: 1. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ads = v il and repeat = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , be n = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if be n was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). 6. "x" denotes left or right port. the diagram is with respect to that port. timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (2,6) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5617 drw 07 (5) (1) ce 1 be n (3) t sb t hb t sw t hw t sa t ha t dc t dc (4) t sc t hc t sb t hb
6.42 13 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5617 drw 08 timing waveform of a multi-device pipelined read (1,2) notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70v3599/89 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. be n , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w and repeat = v ih . timing waveform of a multi-device flow-through read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5617 drw 09 d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1)
6.42 14 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s clk "a" r/ w "a" address "a" data in"a" clk "b" r/ w "b" address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t co (3) t cd2 no match valid no match match match valid 5617 drw 10 t dc timing waveform of left port write to pipelined right port read (1,2,4) notes: 1. ce 0 , be n , and ads = v il ; ce 1 and repeat = v ih . 2. oe = v il for port "b", which is being read from. oe = v ih for port "a", which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (ie, time from write to val id read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on oppos ite port will be t co + t cyc2 + t cd2 ). 4. all timing is the same for left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a" timing waveform with port-to-port flow-through read (1,2,4) data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cd1 t dc data out "b" 5617 drw 11 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t co t dc t sa t sw t ha (3) notes: 1. ce 0 , be n, and ads = v il ; ce 1 and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (i.e., time from write to v alid read on opposite port will be t co + t cyc + t cd1 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (i.e., time from write to valid read on oppo site port will be t co + t cd1 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a".
6.42 15 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5617 drw 12 qn qn + 3 data out ce 1 be n t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n , and ads = v il ; ce 1 and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5617 drw 13 data out qn qn + 4 ce 1 be n oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n , and ads = v il ; ce 1 and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows.
6.42 16 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s timing waveform of flow-through read-to-write-to-read ( oe = v il ) (2) timing waveform of flow-through read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n, and ads = v il ; ce 1 and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 6517 drw 14 qn data out ce 1 be n t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (3) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (3) data in dn + 2 ce 0 clk 5617 drw 15 qn data out ce 1 be n t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (1) dn + 3 t ohz t sw t hw oe t oe
6.42 17 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5617 drw 16 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 timing waveform of pipelined read with address counter advance (1) notes: 1. ce 0 , oe , be n = v il ; ce 1 , r/ w , and repeat = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of flow-through read with address counter advance (1) address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5617 drw 17 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 18 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s address an d 0 t ch2 t cl2 t cyc2 q last q last+1 last ads load clk data in r/ w repeat 5617 drw 19 internal (3) address ads cnten t srpt t hrpt t sd t hd t sw t hw execute repeat write last ads address read last ads address read last ads address + 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha last ads +1 an an + 1 (4) (5) (6) ax t sad t had t scn t hcn timing waveform of write with address counter advance (flow-through or pipelined inputs) (1) timing waveform of counter repeat (2) notes: 1. ce 0 , be n , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce 0 , be n = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during repeat operation. a read or write cycle may be coincidental with the counter repeat cycle: address loaded by last valid ads load will be accessed. extra cycles are shown here simply for clarification. for more information on repeat function refer to truth table ii. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5617 drw 18 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hcn
6.42 19 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s functional description the idt70v3599/89 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asyn- chronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v3599/89s for depth expansion configurations. two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. 5617 drw 20 idt70v3599/89 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 17 /a 16 (1) ce 1 ce 0 v dd v dd idt70v3599/89 idt70v3599/89 idt70v3599/89 control inputs control inputs control inputs control inputs be , r/ w , oe , clk, ads , repeat , cnten depth and width expansion the idt70v3599/89 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v3599/89 can also be used in applications requiring expanded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. figure 4. depth and width expansion with idt70v3599/89 note: 1. a 17 is for idt70v3599, a 16 is for idt70v3589.
6.42 20 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s jtag ac electrical characteristics (1,2,3,4) 70v3599/89 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc j tag data outp ut ho ld 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5617 tbl 12 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. jtag timing specifications tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5617 drw 21 , figure 5. standard jtag timing notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo.
6.42 21 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x0312 (1) defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5617 tbl 13 note: 1. device id for idt70v3589 is 0x0313. scan register sizes register name bit size instruction (ir) 4 bypass (byr) 1 id entificatio n (idr) 32 boundary scan (bsr) note (3) 5617 tbl 14 system interface parameters instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan registe r (bsr) between tdi and tdo. b y pa s s 1111 p lac e s the b y p as s re g i s te r (b yr) b e twe e n tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0011 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5617 tbl 15 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
6.42 22 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s ordering information idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device vo lt ag e i /o input capacitance input duty cycle requirement maximum frequency jitter tolerance 70v3599/89 3.3/2.5 lvttl 8pf 40% 166 75ps idt5v2528 5617 tbl16a idt clock solution for idt70v3599/89 dual-port note: 1. green parts available. for specific speeds, packages and powers contact your local sales office.
6.42 23 high-speed 3.3v 128/64k x 36 dual-port synchronous static ram industrial and commercial temperature ran ges idt70v3599/89s the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dua lporthelp@idt.com www.idt.com datasheet document history: 06/02/00: initial public offering 07/12/00: added mux to functional block diagram 07/30/01: page 20 changed maximum value for jtag ac electrical characteristics for t jcd from 20ns to 25ns page 9 added industrial temperature dc parameters 11/20/01: pages 2, 3 & 4 added date revision for pin configurations page 11 changed t oe value in ac electrical characteristics, please refer to errata #smen-01-05 pages 1 & 22 replaced tm logo with ? logo page 10 changed ac test conditions input rise/fall times 07/01/02: consolidated multiple devices into one datasheet pages 1 & 5 added dcd capability for pipelined outputs page 7 clarified t bias and added t jn page 9 changed dc electrical parameters page 11 removed clock rise & fall time from ac electrical characteristics table removed preliminary status 05/19/03: page 11 added byte enable setuptime & byte enable hold time to ac elecctrical characteristics table page 22 added idt clock solution table 01/10/06: page 1 added green availability to features page 5 changed footnote 2 for truth table i from ads , cnten , repeat = v ih to ads , cnten , repeat = x page 22 added green indicator to ordering information 07/25/08: page 9 corrected a typo in the dc chars table 01/19/09: page 22 removed "idt" from orderable part number 07/26/10: page 11 in order to correct the header notes of the ac elect chars table and align them with the industrial temp range values located in the table, the commercial ta header note has been removed pages 13-16 in order to correct the footnotes of timing diagrams, cnten has been removed to reconcile the footnotes with the cnten logic definition found in truth table ii - address counter control 10/14/14: page 22 added tape & reel to ordering information ?

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